Such a device is well known in the art, for instance from the book "Digital Communications - Fundamentals and Applications" by Bernard Sklar, Prentice-Hall International Editions 1988, paragraph 5.6.4.
The device described therein performs the polynomial division on a bit by bit basis making use of clocked shift registers, thus implying that the rate of a clock controlling these shift registers has to be equal to the arrival rate of the bits of the first sequence at an input of the device. In current communication systems where such a device is used to detect bit errors by using for instance a cyclic redundancy check algorithm wherein such a division is performed, this rate can be relatively high, e.g. 600 Mbit/s, for an ATM network.